How can I do a pause of 2Hz in a clock in VHDL? -

i'm tecnically new in vhdl, , need pause of 2hz or 0.5hz in vhdl program counter project.

on other hand, have following code:

architecture behavior of counter signal q: std_logic_vector(7 downto 0);  begin process(clock, choose)   begin      if clear = '1'         q <= q - q;     else         if rising_edge(clock)             -- when choose '1', process if increment             if(choose = '1')                 case incodec                                when "001" => q <= q + 1;                     when "011" => q <= q + 10;                     when "111" => q <= q + 11;                     when others => q <= q;                 end case;             -- when choose '0', process if decrement             elsif choose = '0'                 case incodec                                when "001" => q <= q - 1;                     when "011" => q <= q - 10;                     when "111" => q <= q - 11;                     when others => q <= q;                 end case;             end if;         end if;     end if;     case q(7 downto 4)                                   --  6543210         when "0000" => hex7 <= "1000000"; --0         when "0001" => hex7 <= "1111001"; --1         when "0010" => hex7 <= "0100100"; --2         when "0011" => hex7 <= "0110000"; --3         when "0100" => hex7 <= "0011001"; --4         when "0101" => hex7 <= "0010010"; --5         when "0110" => hex7 <= "0000010"; --6         when "0111" => hex7 <= "1111000"; --7         when "1000" => hex7 <= "0000000"; --8         when "1001" => hex7 <= "0010000"; --9         when "1010" => hex7 <= "0001000"; --10/a         when "1011" => hex7 <= "0000011"; --11/b/b         when "1100" => hex7 <= "1000110"; --12/c         when "1101" => hex7 <= "0100001"; --13/d/d         when "1110" => hex7 <= "0000110"; --14/e         when "1111" => hex7 <= "0001110"; --15/f         when others => hex7 <= "0111111"; -- -     end case;      case q(3 downto 0)                                   --  6543210         when "0000" => hex6 <= "1000000"; --0         when "0001" => hex6 <= "1111001"; --1         when "0010" => hex6 <= "0100100"; --2         when "0011" => hex6 <= "0110000"; --3         when "0100" => hex6 <= "0011001"; --4         when "0101" => hex6 <= "0010010"; --5         when "0110" => hex6 <= "0000010"; --6         when "0111" => hex6 <= "1111000"; --7         when "1000" => hex6 <= "0000000"; --8         when "1001" => hex6 <= "0010000"; --9         when "1010" => hex6 <= "0001000"; --10/a         when "1011" => hex6 <= "0000011"; --11/b/b         when "1100" => hex6 <= "1000110"; --12/c         when "1101" => hex6 <= "0100001"; --13/d/d         when "1110" => hex6 <= "0000110"; --14/e         when "1111" => hex6 <= "0001110"; --15/f         when others => hex6 <= "0111111"; -- -     end case; end behavior 

when program compile show following error:

error (10818): can't infer register "q[0]" @ counter.vhd(28) because not hold value outside clock edge don't know means

help me please :(

your code contains multiple mistakes:

• don't use synopsys packages arithmetic operations.
  use package numeric_std , types signed and/or unsigned instead.
• q represents state , synthesized flip-flops.
  on fpga technology, initialize them: := (others => '0')
• clear asynchronous signal, list in sensitivity list.
• choose synchronous signal, don't list in sensitivity list.
• when want add numbers 1,2,3 use proper integer literals or specify literal explicitly binary. default decimal.
• using variables shorten code eliminating duplication.
• clearing q should done assigning zeros aggregate: (others => '0').
• a loop , variable can further reduce code , remove big section of duplicated code.
• user variable hex remove additional register stage, not intended designers.
• you commented segment names of 7-segment display 6543210, segments named gfedcba.
• you should put 7-segment decoder separate entity or function increase reuseability.
• your 7-segment display code low-active, designers should write high-active code. low-activeness due board or display design , not responsibility of decoder. inversion can done when assigning hex hex7.

here improved code:

library ieee; use     ieee.std_logic_1164.all; use     ieee.numeric_std.all;   entity counter     -- ... end entity;   architecture behavior of counter     signal q : unsigned(7 downto 0) := (others => '0'); begin     process(clock, clear)         variable decoded : positive;         variable hex     : std_logic_vector(13 downto 0);     begin         case incodec                        when "001" =>  decoded := 1;             when "011" =>  decoded := 2;             when "111" =>  decoded := 3;             when others => decoded := 0;         end case;          if clear = '1'             q <= (others => '0');         elsif rising_edge(clock)             if(choose = '1')     -- when choose '1', process if increment                 q <= q + decoded;             elsif (choose = '0') -- when choose '0', process if decrement                 q <= q - decoded;             end if;         end if;          in 0 1 loop             case q(i*4+7 downto i*4)            --  6543210                 when "0000" => hex(i*7+6 downto i*7) := "1000000"; --0                 when "0001" => hex(i*7+6 downto i*7) := "1111001"; --1                 when "0010" => hex(i*7+6 downto i*7) := "0100100"; --2                 when "0011" => hex(i*7+6 downto i*7) := "0110000"; --3                 when "0100" => hex(i*7+6 downto i*7) := "0011001"; --4                 when "0101" => hex(i*7+6 downto i*7) := "0010010"; --5                 when "0110" => hex(i*7+6 downto i*7) := "0000010"; --6                 when "0111" => hex(i*7+6 downto i*7) := "1111000"; --7                 when "1000" => hex(i*7+6 downto i*7) := "0000000"; --8                 when "1001" => hex(i*7+6 downto i*7) := "0010000"; --9                 when "1010" => hex(i*7+6 downto i*7) := "0001000"; --10/a                 when "1011" => hex(i*7+6 downto i*7) := "0000011"; --11/b                 when "1100" => hex(i*7+6 downto i*7) := "1000110"; --12/c                 when "1101" => hex(i*7+6 downto i*7) := "0100001"; --13/d                 when "1110" => hex(i*7+6 downto i*7) := "0000110"; --14/e                 when "1111" => hex(i*7+6 downto i*7) := "0001110"; --15/f                 when others => hex(i*7+6 downto i*7) := "0111111"; -- -             end case;         end loop;          hex7 <= hex(13 downto 7);         hex6 <= hex(6 downto 0);     end process; end architecture;